Dolphin Technology maintains a broad portfolio of SoC building blocks that provide silicon proven IP for customers who need:

• Memory Interface IPs:
• SDRAM DDR PHY
• SDRAM DDR Controller
• LPDDR 5/4x/4/3/2
• DDR 4/3/2
• Combo Controllers
• EMMC/SD2.0 PHY & Controller
• SD-SDIO4.0/UHS-II PHY & Controller
• Memory Test & Repair (MBIST)
• Octal SPI Controller and PHY
• Quad SPI Controller and PHY

Dolphin's extensive offerings have met the most rigorous standards of the industry's most demanding companies.

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SDRAM DDR Controller

Dolphin Technology offers a high performance DDRx/LPDDRx DRAM memory controller solution that is optimized to provide a complete solution along with our DDR PHY IP.

Our controllers are DFI 4.0 compliant and are fully configurable, ensuring maximum performance across different system environments.

eMMC/SD2.0 PHY & Controller

Dolphin Technology delivers custom, synthesizable IP to support specific design requirements. The DTI EMMC controller provides the logic to integrate a Host and PHY controller supporting embedded MultiMediaCard (eMMC) version 5.1 into any system on chip (SoC).

SD-SDIO4.0/UHS2 PHY & Controller

DTI SD host controller facilitates host equipment to communicate with SD card. It supports both legacy and ultra-high speed II (UHS-II) interfaces.

Memory Test & Repair (MBIST)

Dolphin Technology now provides a memory BIST solution which has been optimized for Dolphin memories. It supports all Dolphin memory compilers, including SRAM and RF.

Octal SPI Controller

Dolphin Octa SPI Controller and PHY IP supports the fastest access frequency of 200MHz, with DDR Mode and Double Transfer Rate (DTR) Protocol enabling data transfer rates up to 400Mbps with reduced read latency, including support for Octal DDR protocol with DQS for Octal SPI devices. The Controller and PHY IP connects to a system-on-chip (SoC) host through an AMBA® APB bus for the register interface and optional DMA peripheral interface.

Quad SPI Controller

Dolphin Technology provides Quad SPI Controller IP which enables access to a QSPI flash device through read, write and erase operations. The Quad SPI IP either controls a serial data link as a master, or reacts to a serial data link as a slave. The core operates in various data modes from 4 bits to 32 bits. The data is then serialized and then transmitted, either LSB or MSB first, using the standard 4-wire SPI bus interface or the extended Quad mode bus.