Quad SPI Controller
Dolphin Technology provides Quad SPI Controller IP which enables access to a QSPI flash device through read, write and erase operations. The Quad SPI IP either controls a serial data link as a master, or reacts to a serial data link as a slave. The core operates in various data modes from 4 bits to 32 bits. The data is then serialized and then transmitted, either LSB or MSB first, using the standard 4-wire SPI bus interface or the extended Quad mode bus.
Quad SPI Controller IP supports many type of QSPI device from different vendors such as Micron Xccela, APMemory PSRAM, Cypress, Windbond, Adesto, Macronix,... This IP can be used flexibly in any application and high performance.
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- Features
- Design Status
- Compliant with the following specifications:
- AMBA, Advanced Peripheral Bus (APB) Specification Version 2.0
- AMBA, Advanced High-performance Bus (AHB) Specification Version 2.0
- AMBA, Advanced eXtensibale Bus (AXI) Specification Version 4.0
- AMBA, Advanced eXtensibale Lite Bus (AXI-Lite) Specification Version 4.0
- DTI Quad-SPI Controller supports:
- Master only operation
- Slave only operation
- Master and slave operation
- Clock synchronization
- Programmable FIFO watermarks
- Interrupt interface
- Data Sheets are available under NDA
- REQUEST NDA