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Home   >  Standard Cell  >  55ULP_EMF
  • Memory
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  • DDR PHY
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Standard Cell

TSMC 55ULP_EMF - Standard Cell Libraries

Dolphin offers an extensive array of Standard Cell libraries that have been methodically tested and verified in silicon for each process technology supported. More than 5000 fully customizable cells are available, and each one has been optimized for speed, routability, power and density, in order to maximize performance and wafer yield while lowering overall SoC cost.

Dolphin's Standard Cell libraries are designed to meet a wide range of application requirements, including:

  • 6-track, Ultra High Density
  • 7-track, Ultra Low Power & Ultra High Density
  • 10-track, High Performance & High Density
  • Channel Lengths include 60nm and 65nm

   Download Product Overview
  • Ultra High Density
  • Ultra Low Power / Ultra High Density
  • High Performance / High Density
  • 6 Track
  • 7 Track
  • 10 Track

All tracks available with Channel Lengths of 60nm & 65nm

Ultra High Density

  • Description
  • Design Status
  • Silicon Status
  • Fully customizable standard cell library consisting of more than 5000 cells
  • 6-track layout
  • Multi-VT (SVT, HVT, LVT) available
  • Multi-channel libraries available
  • NLDM and CCS models available
  • Support for all industry-standard tools (i.e. Magma, Cadence, Synopsys)

Front End views are available under NDA

REQUEST NDA



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Ultra Low Power / Ultra High Density

  • Description
  • Design Status
  • Silicon Status
  • Fully customizable standard cell library consisting of about 5000 cells
  • Single metal layer design for high routing utilization
  • 7-track layout
  • High speed with high density
  • Accurate timing and power models
  • Complete models and views for synthesis and functional simulation tools

Front End views are available under NDA

REQUEST NDA

In production

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High Performance / High Density Standard Cell

  • Description
  • Design Status
  • Silicon Status
  • Fully customizable standard cell library consisting of about 5000 cells
  • Single metal layer design for high routing utilization
  • 10-track layout
  • High speed with high density
  • Accurate timing and power models
  • Complete models and views for synthesis and functional simulation tools

Front End views are available under NDA

REQUEST NDA

In production

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