I2C/I3C PHY & Controller
DTI I2C/I3C Controller provides the logic consistent with NXP I2C/I3C specification to support the communication of low-speed integrated circuits through I2C/I3C bus.
The IP facilitates software controllable by application processor through industry-standard AMBA interface. The bus interface is flexible and easily integrated into APB, AHB or AXI system bus.
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I2C
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Features
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Design Status
- Compliant with the following specifications:
- I2C Bus Specification Version 6.0
- AMBA, Advanced Peripheral Bus (APB) Specification Version 2.0
- DTI I2C Controller supports:
- Master only operation
- Slave only operation
- Master and slave operation
- 5 speed modes:
- Standard speed mode (up to 100 Kbps)
- Fast speed mode (up to 400 Kbps)
- Fast speed mode plus (up to 1 Mbps)
- High speed mode (up to 3.4 Mbps)
- Ultra fast speed mode (up to 5 Mbps)
- Singled or combined message protocol
- 7-bit or 10-bit addressing
- Input spike suppression
- Clock synchronization
- Slave clock stretching
- Bus arbitration
- General call address
- Bus clear operation
- Read device ID
- Programmable timing parameters, including (tLOW), (tHIGH), (tHD;STA), (tSU;STA), (tHD;DAT), (tSU,STO), (tBUF), and (tSP)g
- Programmable FIFO watermarks
- Interrupt interface
- DMA hand-shaking interface
- Software interface consistent with AMBA Advanced Peripheral Bus (APB), configurable bus width 8/16/32
- Data Sheets are available under NDA
- REQUEST NDA
I3C
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Features
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Design Status
- Compliant with the following specifications:
- MIPI I3C specification v1.0
- AMBA, Advanced Peripheral Bus (APB) Specification Version 2.0
- AMBA, Advanced eXtensibale Bus (AXI) Specification Version 4.0
- AMBA, Advanced High-performance Bus (AHB) Specification Version 2.0
- DTI I3C Controller supports:
- Two wire serial interface up to 12.5 MHz using Push-Pull
- Legacy I2C Device co-existence on the same Bus (with some limitations)
- Dynamic Addressing while supporting Static Addressing for Legacy I2C Devices
- Legacy I2C messaging
- I2C-like Single Data Rate Messaging (SDR)
- Optional High Data Rate Messaging Modes (HDR-DDR, HDR-TSL, HDR-TSP)
- Support for Multi-master (transferring the ownership of the bus to a Secondary Master if Present)
- Reception of In-band Interrupt Support from the I3C Slave devices
- Reception of Hot-Join from newly added I3C Slave devices
- Synchronous Timing Support and Asynchronous Time Stamping
- Master only operation
- Slave only operation
- Master and slave operation
- Data Sheets are available under NDA
- REQUEST NDA