Memory Products
TSMC 22ULL - Memory Compilers & Specialty Memory
Dolphin provides a wide range of Memory Compilers and Specialty Memory (ROM, Multi-Port RF, CAM, etc.) optimized to meet even the most demanding requirements for high performance, high density and low power. The compilers enable SoC designers to generate macros with varying aspect ratios, redundancy schemes, VT variations and more.
Download Product Overview
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High Performance (HP)
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High Density (HD)
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Ultra Low Leakage (ULL)
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Dual Rail (DP)
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Power Gating (PG)
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Specialty Memory
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Type
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Depth
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Width
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Single Instance
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Single Port SRAM
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Up to 8K words deep
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Up to 288 bit
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Up to 288 Kbit
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Dual Port SRAM
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Up to 8K words deep
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Up to 144 bit
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Up to 144 Kbit
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Pseudo 2 Port SRAM
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Up to 8K words deep
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Up to 288 bit
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Up to 288 Kbit
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1 Port RF
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Up to 1K words deep
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Up to 576 bit
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Up to 144 Kbit
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2 Port RF
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Up to 1K words deep
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Up to 288 bit
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Up to 72 Kbit
SRAM/RF Features
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Description
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Design Status
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Silicon Status
- Synchronous reads/writes
- Static design with zero standby current (except transistor leakage)
- Ability to compile to multiple aspect ratios
- RAMpiler+® with row and column redundancy of up to 2 quad rows & 2 columns I/O
- No restriction and Fully routable over the array with higher metal layers
- Small set-up and zero hold times
- Power ring size based on frequency of operation and load
- Multiple pin placement and layer options
- Multiple power ring metal layer and configuration options
- Register output options
- Pos. or Neg. Clock Edge
- Multiple output drive strengths
- Different power ring design configurations
- Power ring based on frequency
- Power Mesh on different Metal layers
- Bit Write Mask, Byte Write or Word (global write) options
- Write through, transparent write
- BIST Mux option on inputs
- Row redundancy (RAMpiler+®)
- Column I/O redundancy (RAMpiler+®)
- ECC enabled and capable (SEC, SECDED, OP, EP)
- Front End views are available under NDA
- REQUEST NDA
- Testchip T/O Sep '11
- Testchip report
available
Specialty Memory
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Description
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Design Status
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Silicon Status
Read Only Memory Compilers
- Diffusion ROM compiler
- Via Programmable ROM compiler
- Front End views are available under NDA
- REQUEST NDA
Content Addressable Memory Compilers
- Binary BCAM, Ternary TCAM, and CAM compilers using CAMpiler® technology
- Front End views are available under NDA
- REQUEST NDA
Specialty Memory
- Custom Register Files with different configurations such as: 1W/4R, 3W/3R, 1W/8R, 2W/4R, 3W/5R, etc.
- Front End views are available under NDA
- REQUEST NDA
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Category
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Description
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High Performance
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Uses high-current bit cells, for customers who require high performance
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High Density
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Uses high density bit cells, for customers requiring the lowest area profile
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Ultra Low Leakage
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Significantly reduces leakage power while retaining all contents of memory
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Dual Rail
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For reduced active & leakage power; periphery and array are run at separate voltages
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Power Gating
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Significantly reduces leakage power without retaining memory contents