Memory Controller
Dolphin Technology offers high performance DDR4/3/2 SDRAM and LPDDR3/2 SDRAM Memory Controller IP across a broad range of process technologies.
These Memory Controllers are fully compliant with the DFI 3.1 specification, support speeds up to 3200 Mpbs, and are optimized to provide a comprehensive solution when combined with Dolphin's DDR PHY IP.
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Features
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Design Status
- Optimized to provide a complete solution along with the Dolphin Technology DDR PHY solution
- DFI 3.1 Interface with Matching or 1:2 Frequency Ratio
- Built-in Gate Training, Read/Write Leveling Functionality
- Supports speeds of up to 3200Mbps
- Supports JEDEC Standard DDR4/3/2 and LPDDR3/2 SDRAM
- Multi-Port Configurable AXI4 Interface with QoS Signaling
- Fully compliant with the DDR PHY Interface (DFI) 3.1 Specification
- Multi-port arbitration engine with programmable dynamic priority algorithm ensure high performance and low-latency.
- Pipeline Option for Frequency versus Latency Tradeoff
- Supports core speed up to 1066MHz on TSMC 40G process.
- Fully configurable for various performances and requirements, ensuring maximum performance for different system environments.
- FPGA portable. Compatible with Xilinx PHY and Altera PHY.
- Available with BFM verification suite.
- Single AXI4-Lite Programming Interface
- Support for AXI4 Dynamic QoS Signaling for Non-Blocking Communications
- Support for Low-Latency Bypass Ports/Channels
- Advanced Dynamic QoS Support Based on the Queuing Theory and Traffic Hysteresis
- Forward Priority Propagation for Queued Transactions
- Traffic-Configurable Address Mapping Scheme with Two Column Segments
- Run-time Configurable Timing Parameters and Memory Settings
- Intelligent Bank Management and Auto-Precharge Scheduling
- Intelligent Traffic Direction Aggregation and Switching
- Programmable and Dynamic Auto-refresh Scheduling
- Proprietary Non-Blocking Priority-Based DDRx/LPDDRx SDRAM Control and Data Buses Access Algorithm
- Real-Time QoS Capability
- Multi-Channel Configuration (Up to 4)
- Support for Out-of-Order Memory Access
- Data Sheets are available under NDA
- REQUEST NDA