I/O Products
UMC
- GPIO
- DDR
- Specialty Purpose
GPIO
- Description
- Design Status
- Silicon Status
- Pad design with 25um pitch
- I/O Drive strengths 2/4/6/8/10/12 mA 0.9V core with 2.5V Xtrs, 2.5V output Drive/3.3V tolerant
- I/O Drive strengths 2/4/6/8/10/12 mA 0.9V core with 2.5V Xtrs, 3.3V output Drive Capable
- I/O Drive strengths 2/4/6/8/10/12 mA 0.9V core with 2.5V Xtrs, 2.5V output Drive
- 4 different slew rate options
- Built-in JTAG Logic for testability (LogicVision, Mentor or Synopsys compatible)
- input/output registers options
- sustain and pull-up/down options
- Level shifts from 0.9V core voltage up to 2.5V/3.3V I/O supply and from 2.5V/3.3V to 0.9V
Front End views are
available under NDA
Test Chip
Taped Chip
( Oct 2007 )
DDR
- Description
- Design Status
- Silicon Status
- Pad design with 25um pitch
- DDR I, SSTL 2.5V (Class I/II) with PVT (Process, Voltage and Temperature) Compensation and optional PVT compensated internal termination RTT upto @400-500MHz/800Mbps-1Gbps
- DDR II, SSTL 1.8V (Class I/II) with PVT Compensation and optional PVT compensated internal termination RTT upto @400-500MHz/800Mbps-1Gbps
- DDR III, SSTL 1.5V (Class I/II) with PVT Compensation and optional PVT compensated internal termination RTT
- HSTL 1.8V/1.5V (Class I/II) with PVT Compensation Impedance Matched, Source Series Terminated 1.5V IO (SDR/DDR) with PVT compensation
- Impedance Matched, Source Series Terminated 1.8V IO (SDR/DDR) with PVT Compensation
- Impedance Matched, Source Series Terminated 2.5V IO (SDR/DDR) with PVT Compensation
- Impedance Matched, Source Series Terminated 3.3V IO (SDR/DDR) with PVT Compensation
Front End views are
available under NDA
Test Chip
Taped Chip
( Oct 2007 )
Special Purpose
- Description
- Design Status
- Silicon Status
- Pad design with 25um pitch
- DDR I, SSTL 2.5V (Class I/II) with PVT (Process, Voltage and Temperature) Compensation and optional PVT compensated internal termination RTT upto @400-500MHz/800Mbps-1Gbps
- DDR II, SSTL 1.8V (Class I/II) with PVT Compensation and optional PVT compensated internal termination RTT upto @400-500MHz/800Mbps-1Gbps
- DDR III, SSTL 1.5V (Class I/II) with PVT Compensation and optional PVT compensated internal termination RTT
- HSTL 1.8V/1.5V (Class I/II) with PVT Compensation
Impedance Matched, Source Series Terminated 1.5V IO (SDR/DDR) with PVT compensation - Impedance Matched, Source Series Terminated 1.8V IO (SDR/DDR) with PVT Compensation
- Impedance Matched, Source Series Terminated 2.5V IO (SDR/DDR) with PVT Compensation
- Impedance Matched, Source Series Terminated 3.3V IO (SDR/DDR) with PVT Compensation
- LVPECL IO with PVT Compensation
- LVDS/LVPECL Combo with PVT Compensation
- PCI
- I2C
Front End views are
available under NDA
Test Chip
Taped Chip
( Oct 2007 )