DDR PHY
DDR PHY
Dolphin Technology now provides customers with a DDR PHY Interface(DFI) solution.
We now provide a complete DDR Memory Controller Solution.
- Features
- Dolphin DDR2/DDR3 PHY IP is fully compliant with the DFI 2.0 Specification
- Supports speeds of up to 1600Mbps for 2.5V Oxide and 2000Mbps for 1.8V oxide
- IP is split into 2 hard macros. One for commands and address and another for 8-bit data bus.
Can support custom number of address bits. - Compensation controller and Pads are provided for automatic driver and receiver termination impedance calibration
- Features include slew rate control, Per-bit de-skew, gate training, read and write leveling.
- JTAG signals also provided for Mentor/Synopsys and LogicVision
- Loopback functionality provided which is compatible to Northwest Logic Controller
- Macro requires 2 clocks. A core clock and a transmit clock that can be in 1:1, 1:2 or 1:4 ratio
- Can be used in wirebond, flip-chip and cup configurations
- Tested functionally with Denali, Eureka Technology & Northwest Logic controllers