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Home   >  Memory Products  >  0.13LVOD

Memory Products

TSMC

  • High
    Performance SRAM
  • High
    Performance RF
  • Ultra
    Low Leakage
    SRAM
  • High
    Density SRAM
  • High
    Density RF

  • Specialty Memory
  • SP     DP
  • 1P     2P
  • SP     DP
  • SP     DP
  • 1P     2P
  • ROM Multi - Port RF CAM

High Performance

  • Description
  • Design Status
  • Silicon Status

Single Port Memory Compilers

  • Synchronous reads/writes
  • Static design with zero standby current (except transistor leakage)
  • Ability to compile to multiple aspect ratios
  • RAMpiler+® with row and column redundancy of up to 2 quad rows & 2 columns I/O
  • No restriction and Fully routable over the array with higher metal layers
  • Small set-up and zero hold times
  • Power ring size based on frequency of operation and load
  • Up to 1.1 Mbit single instance
  • Up to 288 bit word
  • Up to 16K words deep
  • Multiple pin placement and layer options
  • Multiple power ring metal layer and configuration options
  • Register output options
  • Pos. or Neg. Clock Edge
  • Multiple output drive strengths
  • Different power ring design configurations
  • Power ring based on frequency
  • Power Mesh on different Metal layers
  • Bit Write Mask, Byte Write or Word (global write) options
  • Write through, transparent write
  • BIST Mux option on inputs
  • Row redundancy (RAMpiler+®)
  • Column I/O redundancy (RAMpiler+®)
  • ECC enabled and capable (SEC, SECDED, OP, EP)
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  • Front End views are
  • available under NDA

Dual Port Memory Compilers

  • Synchronous reads/writes
  • Static design with zero standby current (except transistor leakage)
  • Ability to compile to multiple aspect ratios
  • RAMpiler+® with row and column redundancy of up to 2 quad rows & 2 columns I/O
  • No restriction and Fully routable over the array with higher metal layers
  • Small set-up and zero hold times
  • Power ring size based on frequency of operation and load
  • Up to 1.1 Mbit single instance
  • Up to 288 bit word
  • Up to 16K words deep
  • Multiple pin placement and layer options
  • Multiple power ring metal layer and configuration options
  • Register output options
  • Pos. or Neg. Clock Edge
  • Multiple output drive strengths
  • Different power ring design configurations
  • Power ring based on frequency
  • Power Mesh on different Metal layers
  • Bit Write Mask, Byte Write or Word (global write) options
  • Write through, transparent write
  • BIST Mux option on inputs
  • Row redundancy (RAMpiler+®)
  • Column I/O redundancy (RAMpiler+®)
  • ECC enabled and capable (SEC, SECDED, OP, EP)
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  • Front End views are
  • available under NDA
Top      

High Performance

  • Description
  • Design Status
  • Silicon Status

Single Port Memory Compilers

  • Synchronous reads/writes
  • Static design with zero standby current (except transistor leakage)
  • Ability to compile to multiple aspect ratios
  • RAMpiler+® with row and column redundancy of up to 2 quad rows & 2 columns I/O
  • No restriction and Fully routable over the array with higher metal layers
  • Small set-up and zero hold times
  • Power ring size based on frequency of operation and load
  • Up to 1.1 Mbit single instance
  • Up to 288 bit word
  • Up to 16K words deep
  • Multiple pin placement and layer options
  • Multiple power ring metal layer and configuration options
  • Register output options
  • Pos. or Neg. Clock Edge
  • Multiple output drive strengths
  • Different power ring design configurations
  • Power ring based on frequency
  • Power Mesh on different Metal layers
  • Bit Write Mask, Byte Write or Word (global write) options
  • Write through, transparent write
  • BIST Mux option on inputs
  • Row redundancy (RAMpiler+®)
  • Column I/O redundancy (RAMpiler+®)
  • ECC enabled and capable (SEC, SECDED, OP, EP)
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  • Front End views are
  • available under NDA

Dual Port Memory Compilers

  • Synchronous reads/writes
  • Static design with zero standby current (except transistor leakage)
  • Ability to compile to multiple aspect ratios
  • RAMpiler+® with row and column redundancy of up to 2 quad rows & 2 columns I/O
  • No restriction and Fully routable over the array with higher metal layers
  • Small set-up and zero hold times
  • Power ring size based on frequency of operation and load
  • Up to 1.1 Mbit single instance
  • Up to 288 bit word
  • Up to 16K words deep
  • Multiple pin placement and layer options
  • Multiple power ring metal layer and configuration options
  • Register output options
  • Pos. or Neg. Clock Edge
  • Multiple output drive strengths
  • Different power ring design configurations
  • Power ring based on frequency
  • Power Mesh on different Metal layers
  • Bit Write Mask, Byte Write or Word (global write) options
  • Write through, transparent write
  • BIST Mux option on inputs
  • Row redundancy (RAMpiler+®)
  • Column I/O redundancy (RAMpiler+®)
  • ECC enabled and capable (SEC, SECDED, OP, EP)
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  • Front End views are
  • available under NDA
Top      

High Performance

  • Description
  • Design Status
  • Silicon Status

Single Port Memory Compilers

  • Synchronous reads/writes
  • Static design with zero standby current (except transistor leakage)
  • Ability to compile to multiple aspect ratios
  • RAMpiler+® with row and column redundancy of up to 2 quad rows & 2 columns I/O
  • No restriction and Fully routable over the array with higher metal layers
  • Small set-up and zero hold times
  • Power ring size based on frequency of operation and load
  • Up to 1.1 Mbit single instance
  • Up to 288 bit word
  • Up to 16K words deep
  • Multiple pin placement and layer options
  • Multiple power ring metal layer and configuration options
  • Register output options
  • Pos. or Neg. Clock Edge
  • Multiple output drive strengths
  • Different power ring design configurations
  • Power ring based on frequency
  • Power Mesh on different Metal layers
  • Bit Write Mask, Byte Write or Word (global write) options
  • Write through, transparent write
  • BIST Mux option on inputs
  • Row redundancy (RAMpiler+®)
  • Column I/O redundancy (RAMpiler+®)
  • ECC enabled and capable (SEC, SECDED, OP, EP)
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  •  
  •  
  •  
  •  
  • Front End views are
  • available under NDA

Dual Port Memory Compilers

  • Synchronous reads/writes
  • Static design with zero standby current (except transistor leakage)
  • Ability to compile to multiple aspect ratios
  • RAMpiler+® with row and column redundancy of up to 2 quad rows & 2 columns I/O
  • No restriction and Fully routable over the array with higher metal layers
  • Small set-up and zero hold times
  • Power ring size based on frequency of operation and load
  • Up to 1.1 Mbit single instance
  • Up to 288 bit word
  • Up to 16K words deep
  • Multiple pin placement and layer options
  • Multiple power ring metal layer and configuration options
  • Register output options
  • Pos. or Neg. Clock Edge
  • Multiple output drive strengths
  • Different power ring design configurations
  • Power ring based on frequency
  • Power Mesh on different Metal layers
  • Bit Write Mask, Byte Write or Word (global write) options
  • Write through, transparent write
  • BIST Mux option on inputs
  • Row redundancy (RAMpiler+®)
  • Column I/O redundancy (RAMpiler+®)
  • ECC enabled and capable (SEC, SECDED, OP, EP)
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  •  
  •  
  •  
  • Front End views are
  • available under NDA
Top      

High Performance

  • Description
  • Design Status
  • Silicon Status

Single Port Memory Compilers

  • Synchronous reads/writes
  • Static design with zero standby current (except transistor leakage)
  • Ability to compile to multiple aspect ratios
  • RAMpiler+® with row and column redundancy of up to 2 quad rows & 2 columns I/O
  • No restriction and Fully routable over the array with higher metal layers
  • Small set-up and zero hold times
  • Power ring size based on frequency of operation and load
  • Up to 1.1 Mbit single instance
  • Up to 288 bit word
  • Up to 16K words deep
  • Multiple pin placement and layer options
  • Multiple power ring metal layer and configuration options
  • Register output options
  • Pos. or Neg. Clock Edge
  • Multiple output drive strengths
  • Different power ring design configurations
  • Power ring based on frequency
  • Power Mesh on different Metal layers
  • Bit Write Mask, Byte Write or Word (global write) options
  • Write through, transparent write
  • BIST Mux option on inputs
  • Row redundancy (RAMpiler+®)
  • Column I/O redundancy (RAMpiler+®)
  • ECC enabled and capable (SEC, SECDED, OP, EP)
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  •  
  •  
  •  
  •  
  • Front End views are
  • available under NDA

Dual Port Memory Compilers

  • Synchronous reads/writes
  • Static design with zero standby current (except transistor leakage)
  • Ability to compile to multiple aspect ratios
  • RAMpiler+® with row and column redundancy of up to 2 quad rows & 2 columns I/O
  • No restriction and Fully routable over the array with higher metal layers
  • Small set-up and zero hold times
  • Power ring size based on frequency of operation and load
  • Up to 1.1 Mbit single instance
  • Up to 288 bit word
  • Up to 16K words deep
  • Multiple pin placement and layer options
  • Multiple power ring metal layer and configuration options
  • Register output options
  • Pos. or Neg. Clock Edge
  • Multiple output drive strengths
  • Different power ring design configurations
  • Power ring based on frequency
  • Power Mesh on different Metal layers
  • Bit Write Mask, Byte Write or Word (global write) options
  • Write through, transparent write
  • BIST Mux option on inputs
  • Row redundancy (RAMpiler+®)
  • Column I/O redundancy (RAMpiler+®)
  • ECC enabled and capable (SEC, SECDED, OP, EP)
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  •  
  •  
  •  
  • Front End views are
  • available under NDA
Top      

High Performance

  • Description
  • Design Status
  • Silicon Status

Single Port Memory Compilers

  • Synchronous reads/writes
  • Static design with zero standby current (except transistor leakage)
  • Ability to compile to multiple aspect ratios
  • RAMpiler+® with row and column redundancy of up to 2 quad rows & 2 columns I/O
  • No restriction and Fully routable over the array with higher metal layers
  • Small set-up and zero hold times
  • Power ring size based on frequency of operation and load
  • Up to 1.1 Mbit single instance
  • Up to 288 bit word
  • Up to 16K words deep
  • Multiple pin placement and layer options
  • Multiple power ring metal layer and configuration options
  • Register output options
  • Pos. or Neg. Clock Edge
  • Multiple output drive strengths
  • Different power ring design configurations
  • Power ring based on frequency
  • Power Mesh on different Metal layers
  • Bit Write Mask, Byte Write or Word (global write) options
  • Write through, transparent write
  • BIST Mux option on inputs
  • Row redundancy (RAMpiler+®)
  • Column I/O redundancy (RAMpiler+®)
  • ECC enabled and capable (SEC, SECDED, OP, EP)
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  •  
  •  
  •  
  •  
  •  
  • Front End views are
  • available under NDA

Dual Port Memory Compilers

  • Synchronous reads/writes
  • Static design with zero standby current (except transistor leakage)
  • Ability to compile to multiple aspect ratios
  • RAMpiler+® with row and column redundancy of up to 2 quad rows & 2 columns I/O
  • No restriction and Fully routable over the array with higher metal layers
  • Small set-up and zero hold times
  • Power ring size based on frequency of operation and load
  • Up to 1.1 Mbit single instance
  • Up to 288 bit word
  • Up to 16K words deep
  • Multiple pin placement and layer options
  • Multiple power ring metal layer and configuration options
  • Register output options
  • Pos. or Neg. Clock Edge
  • Multiple output drive strengths
  • Different power ring design configurations
  • Power ring based on frequency
  • Power Mesh on different Metal layers
  • Bit Write Mask, Byte Write or Word (global write) options
  • Write through, transparent write
  • BIST Mux option on inputs
  • Row redundancy (RAMpiler+®)
  • Column I/O redundancy (RAMpiler+®)
  • ECC enabled and capable (SEC, SECDED, OP, EP)
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  •  
  •  
  •  
  •  
  • Front End views are
  • available under NDA
Top      

High Performance

  • Description
  • Design Status
  • Silicon Status

Single Port Memory Compilers

  • Synchronous reads/writes
  • Static design with zero standby current (except transistor leakage)
  • Ability to compile to multiple aspect ratios
  • RAMpiler+® with row and column redundancy of up to 2 quad rows & 2 columns I/O
  • No restriction and Fully routable over the array with higher metal layers
  • Small set-up and zero hold times
  • Power ring size based on frequency of operation and load
  • Up to 1.1 Mbit single instance
  • Up to 288 bit word
  • Up to 16K words deep
  • Multiple pin placement and layer options
  • Multiple power ring metal layer and configuration options
  • Register output options
  • Pos. or Neg. Clock Edge
  • Multiple output drive strengths
  • Different power ring design configurations
  • Power ring based on frequency
  • Power Mesh on different Metal layers
  • Bit Write Mask, Byte Write or Word (global write) options
  • Write through, transparent write
  • BIST Mux option on inputs
  • Row redundancy (RAMpiler+®)
  • Column I/O redundancy (RAMpiler+®)
  • ECC enabled and capable (SEC, SECDED, OP, EP)
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  •  
  •  
  •  
  •  
  •  
  •  
  • Front End views are
  • available under NDA

Dual Port Memory Compilers

  • Synchronous reads/writes
  • Static design with zero standby current (except transistor leakage)
  • Ability to compile to multiple aspect ratios
  • RAMpiler+® with row and column redundancy of up to 2 quad rows & 2 columns I/O
  • No restriction and Fully routable over the array with higher metal layers
  • Small set-up and zero hold times
  • Power ring size based on frequency of operation and load
  • Up to 1.1 Mbit single instance
  • Up to 288 bit word
  • Up to 16K words deep
  • Multiple pin placement and layer options
  • Multiple power ring metal layer and configuration options
  • Register output options
  • Pos. or Neg. Clock Edge
  • Multiple output drive strengths
  • Different power ring design configurations
  • Power ring based on frequency
  • Power Mesh on different Metal layers
  • Bit Write Mask, Byte Write or Word (global write) options
  • Write through, transparent write
  • BIST Mux option on inputs
  • Row redundancy (RAMpiler+®)
  • Column I/O redundancy (RAMpiler+®)
  • ECC enabled and capable (SEC, SECDED, OP, EP)
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  • Front End views are
  • available under NDA
Top      

High Performance

  • Description
  • Design Status
  • Silicon Status
  • Pad design with 25um pitch
  • DDR I, SSTL 2.5V (Class I/II) with PVT (Process, Voltage and Temperature) Compensation and optional PVT compensated internal termination RTT upto @400-500MHz/800Mbps-1Gbps
  • DDR II, SSTL 1.8V (Class I/II) with PVT Compensation and optional PVT compensated internal termination RTT upto @400-500MHz/800Mbps-1Gbps
  • DDR III, SSTL 1.5V (Class I/II) with PVT Compensation and optional PVT compensated internal termination RTT
  • HSTL 1.8V/1.5V (Class I/II) with PVT Compensation
    Impedance Matched, Source Series Terminated 1.5V IO (SDR/DDR) with PVT compensation
  • Impedance Matched, Source Series Terminated 1.8V IO (SDR/DDR) with PVT Compensation
  • Impedance Matched, Source Series Terminated 2.5V IO (SDR/DDR) with PVT Compensation
  • Impedance Matched, Source Series Terminated 3.3V IO (SDR/DDR) with PVT Compensation
  • LVPECL IO with PVT Compensation
  • LVDS/LVPECL Combo with PVT Compensation
  • PCI
  • I2C

Front End views are
available under NDA

Test Chip
Taped Chip
( Oct 2007 )

Top      

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