I/O Products
TSMC 16FF+ (GL & LL)
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GPIO
Dolphin Technology provides a complete GPIO IO library package. The package includes configurable IO's, power cells, fillers, spacers and analog cells. ESD and latch-up prevention structures are built-in into the library
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Description
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Design Status
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Silicon Status
- Pad design (Options include: Tolerant, Capable, Fail Safe, Without Fail Safe)
- Supports wirebond/CUP and flipchip packages
- Programmable metal stack options
- I/O Drive strengths 2/4/6/8/10/12 mA with 1.8V transistor, 1.8V output Drive/3.3V tolerant, also support 1.2V/1.5V output Drive with lower Drive strength
- I/O Drive strengths 2/4/6/8/10/12 mA with 1.8V transistor, 1.8V/2.5V/3.3V output Drive Capable, also support 1.2V/1.5V output Drive with lower Drive strength
- For 33VT IO, 2 different slew rate options; for 33VC IO, 4 different slew rate options
- Built-in JTAG Logic for testability (LogicVision, Mentor or Synopsys compatible)
- Input/Output registers options
- Pull-up/down options
- In-built ESD and Latchup Prevention circuits
DDR
Dolphin Technology provides a complete DDR IO library package. The package includes configurable single-ended and differential IO's, power cells, fillers, spacers and calibration cells. ESD and latch-up prevention structures are built-in into the library
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Description
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Design Status
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Silicon Status
- Pad design
- Supports wirebond/CUP and flipchip packages
- Programmable metal stack options
- DDR4/DDR3/DDR2 and LPDDR3/LPDDR2 I/O with PVT Compensation and PVT compensated internal termination RTT using 1.8V transistor
- Built-in JTAG Logic for testability (LogicVision, Mentor or Synopsys compatible)
- Input/Output registers options
- Pull-up/down options
- In-built ESD and Latchup Prevention circuits
NAND FLASH I/O
Dolphin Technology provides a complete NAND Flash I/O library package compliant with ONFI 4/3/2/1 and Toggle 2/1 NAND specifications. The package includes configurable single-ended and differential IO's, power cells, fillers, spacers and calibration cells. ESD and latch-up prevention structures are built-in into the library
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Description
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Design Status
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Silicon Status
- ONFI 4/3/2/1 and Toggle 2/1 NAND compliant
- Pad design
- Supports wirebond/CUP and flipchip packages
- Programmable metal stack options
- NAND FLASH I/O I/O with PVT Compensation and PVT compensated internal termination RTT using 1.8V transistor
- Drive capability up to 80pF
- Built-in JTAG Logic for testability (LogicVision, Mentor or Synopsys compatible)
- Input/Output registers options
- Pull-up/down options
- In-built ESD and Latchup Prevention circuits
Special Purpose
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Description
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Design Status
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Silicon Status
- LVPECL IO with PVT Compensation
- LVDS/LVPECL Combo with PVT Compensation
- PCI
- I2C
Front End views are available under NDA