Standard Cell
TSMC 40G - Standard Cell Libraries
Dolphin offers an extensive array of Standard Cell libraries that have been methodically tested and verified in silicon for each process technology supported. More than 5000 fully customizable cells are available, and each one has been optimized for speed,
routability, power and density, in order to maximize performance and wafer yield while lowering overall SoC cost.
Dolphin's Standard Cell libraries are available in Multi-VT (SVT, HVT, LVT) and Multi-channel, and are designed to meet a wide range of application requirements, including:
- 6-track, Ultra Low Power & Ultra High Density
- 7-track, Very Low Power & Very High Density
- 10-track, High Performance & High Density
- 12-track, Ultra High Performance & High Density
- Channel Lengths include 40nm, 45nm and 50nm
Download Product Overview
- Ultra Low Power / Ultra High Density
- Ultra High Density
- High Performance / High Density
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Ultra High Performance
All tracks available with Channel Lengths of 40nm, 45nm & 50nm
Ultra Low Power / Ultra High Density
- Description
- Design Status
- Silicon Status
- Fully customizable standard cell library consisting of more than 5000 cells
- 6-track layout
- Multi-VT (SVT, HVT, LVT) available
- Multi-channel libraries available
- NLDM and CCS models available
- Support for all industry-standard tools (i.e. Magma, Cadence, Synopsys)
Very Low Power / Very High Density
- Description
- Design Status
- Silicon Status
- Fully customizable standard cell library consisting of more than 5000 cells
- 7-track layout
- Multi-VT (SVT, HVT, LVT) available
- Multi-channel libraries available
- NLDM and CCS models available
- Support for all industry-standard tools (i.e. Magma, Cadence, Synopsys)
Front End views are available under NDA
Testchip 1 taped out
April 2009
Testchip 2 taped out
May 2010
In production
High Performance / High Density Standard Cell
- Description
- Design Status
- Silicon Status
- Fully customizable standard cell library consisting of more than 5000 cells
- 10-track layout
- Multi-VT (SVT, HVT, LVT) available
- Multi-channel libraries available
- NLDM and CCS models available
- Support for all industry-standard tools (i.e. Magma, Cadence, Synopsys)
Front End views are available under NDA
Testchip 1 taped out
April 2009
Testchip 2 taped out
May 2010
In production
Ultra High Performance
- Description
- Design Status
- Silicon Status
- Fully customizable standard cell library consisting of more than 5000 cells
- 12-track layout
- Multi-VT (SVT, HVT, LVT) available
- Multi-channel libraries available
- NLDM and CCS models available
- Support for all industry-standard tools (i.e. Magma, Cadence, Synopsys)
Front End views are available under NDA
Testchip 1 taped out
April 2009
Testchip 2 taped out
May 2010