Memory Products
TSMC 28HPC+ - Memory Compilers & Specialty Memory
Dolphin provides a wide range of Memory Compilers and Specialty Memory (ROM, Multi-Port RF, CAM, etc.) optimized to meet even the most demanding requirements for high performance, high density and low power. The compilers enable SoC designers to generate macros with varying aspect ratios, redundancy schemes, VT variations and more.
Download Product Overview
- Type
- Depth
- Width
- Single Instance
- Single Port SRAM
- Up to 8K words deep
- Up to 288 bit
- Up to 288 Kbit
- Multi-banks SP SRAM
- Up to 8K x8 words deep
- Up to 288 bit
- Up to 288 x8 Kbit
- Dual Port SRAM
- Up to 8K words deep
- Up to 144 bit
- Up to 144 Kbit
- Pseudo 2 Port SRAMUp to 8K words deepUp to 288 bitUp to 288 Kbit
- 1 Port RFUp to 1K words deepUp to 576 bitUp to 144 Kbit
- 2 Port RF
- Up to 1K words deep
- Up to 288 bit
- Up to 72 Kbit
SRAM/RF Features
- Description
- Design Status
- Silicon Status
- Synchronous reads/writes
- Static design with zero standby current (except transistor leakage)
- Ability to compile to multiple aspect ratios
- RAMpiler+® with row and column redundancy of up to 2 quad rows & 2 columns I/O
- No restriction and Fully routable over the array with higher metal layers
- Small set-up and zero hold times
- Power ring size based on frequency of operation and load
- Multiple pin placement and layer options
- Multiple power ring metal layer and configuration options
- Register output options with scan chain
- Pos. or Neg. Clock Edge
- Multiple output drive strengths
- Different power ring design configurations
- Power ring based on frequency
- Power Mesh on different Metal layers
- Bit Write Mask, Byte Write or Word (global write) options
- Write through, transparent write
- BIST Mux option on inputs
- Row redundancy (RAMpiler+®)
- Column I/O redundancy (RAMpiler+®)
- ECC enabled and capable (SEC, SECDED, OP, EP)
- Front End views are available under NDA
- REQUEST NDA
- Testchip T/O Sep '11
- Testchip report
availableSpecialty Memory
- Description
- Design Status
- Silicon Status
Read Only Memory Compilers
- Diffusion ROM compiler
- Via Programmable ROM compiler
- Front End views are available under NDA
- REQUEST NDA
Content Addressable Memory Compilers
- Binary BCAM, Ternary TCAM, and CAM compilers using CAMpiler® technology
- Front End views are available under NDA
- REQUEST NDA
Specialty Memory
- Custom Register Files with different configurations such as: 1W/4R, 3W/3R, 1W/8R, 2W/4R, 3W/5R, etc.
- Front End views are available under NDA
- REQUEST NDA
- Category
- Description
- High PerformanceUses high-current bit cells, for customers who require high performance
- High DensityUses high density bit cells, for customers requiring the lowest area profile
- Ultra Low LeakageSignificantly reduces leakage power while retaining all contents of memory
- Dual RailFor reduced active & leakage power; periphery and array are run at separate voltages
- Power GatingSignificantly reduces leakage power without retaining memory contents