Memory Products
IBM 6SF - Memory Compilers & Specialty Memory
Dolphin provides a wide range of Memory Compilers and Specialty Memory (ROM, Multi-Port RF, CAM, etc.) optimized to meet even the most demanding requirements for high performance, high density and low power. The compilers enable SoC designers to generate macros with varying aspect ratios, redundancy schemes, VT variations and more.
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| High Performance SRAM | High Performance RF | Ultra Low Leakage SRAM | High Density SRAM | High Density RF | Specialty Memory | |||||||
| SP | DP | 1P | 2P | SP | DP | SP | DP | 1P | 2P | ROM | CAM | |
| Multi-Port RF | ||||||||||||
High Performance SRAM
- Description
- Design Status
- Silicon Status
Single Port Memory Compilers
- Synchronous reads/writes
- Static design with zero standby current (except transistor leakage)
- Ability to compile to multiple aspect ratios
- RAMpiler+® with row and column redundancy of up to 2 quad rows & 2 columns I/O
- No restriction and Fully routable over the array with higher metal layers
- Small set-up and zero hold times
- Power ring size based on frequency of operation and load
- Up to 1.1 Mbit single instance
- Up to 288 bit word
- Up to 16K words deep
- Multiple pin placement and layer options
- Multiple power ring metal layer and configuration options
- Register output options
- Pos. or Neg. Clock Edge
- Multiple output drive strengths
- Different power ring design configurations
- Power ring based on frequency
- Power Mesh on different Metal layers
- Bit Write Mask, Byte Write or Word (global write) options
- Write through, transparent write
- BIST Mux option on inputs
- Row redundancy (RAMpiler+®)
- Column I/O redundancy (RAMpiler+®)
- ECC enabled and capable (SEC, SECDED, OP, EP)
- Front End views are available under NDA
Dual Port Memory Compilers
- Synchronous reads/writes
- Static design with zero standby current (except transistor leakage)
- Ability to compile to multiple aspect ratios
- RAMpiler+® with row and column redundancy of up to 2 quad rows & 2 columns I/O
- No restriction and Fully routable over the array with higher metal layers
- Small set-up and zero hold times
- Power ring size based on frequency of operation and load
- Up to 1.1 Mbit single instance
- Up to 288 bit word
- Up to 16K words deep
- Multiple pin placement and layer options
- Multiple power ring metal layer and configuration options
- Register output options
- Pos. or Neg. Clock Edge
- Multiple output drive strengths
- Different power ring design configurations
- Power ring based on frequency
- Power Mesh on different Metal layers
- Bit Write Mask, Byte Write or Word (global write) options
- Write through, transparent write
- BIST Mux option on inputs
- Row redundancy (RAMpiler+®)
- Column I/O redundancy (RAMpiler+®)
- ECC enabled and capable (SEC, SECDED, OP, EP)
- Front End views are available under NDA
High Performance RF
- Description
- Design Status
- Silicon Status
Single Port Memory Compilers
- Synchronous reads/writes
- Static design with zero standby current (except transistor leakage)
- Ability to compile to multiple aspect ratios
- RAMpiler+® with row and column redundancy of up to 2 quad rows & 2 columns I/O
- No restriction and Fully routable over the array with higher metal layers
- Small set-up and zero hold times
- Power ring size based on frequency of operation and load
- Up to 1.1 Mbit single instance
- Up to 288 bit word
- Up to 16K words deep
- Multiple pin placement and layer options
- Multiple power ring metal layer and configuration options
- Register output options
- Pos. or Neg. Clock Edge
- Multiple output drive strengths
- Different power ring design configurations
- Power ring based on frequency
- Power Mesh on different Metal layers
- Bit Write Mask, Byte Write or Word (global write) options
- Write through, transparent write
- BIST Mux option on inputs
- Row redundancy (RAMpiler+®)
- Column I/O redundancy (RAMpiler+®)
- ECC enabled and capable (SEC, SECDED, OP, EP)
- Front End views are available under NDA
Dual Port Memory Compilers
- Synchronous reads/writes
- Static design with zero standby current (except transistor leakage)
- Ability to compile to multiple aspect ratios
- RAMpiler+® with row and column redundancy of up to 2 quad rows & 2 columns I/O
- No restriction and Fully routable over the array with higher metal layers
- Small set-up and zero hold times
- Power ring size based on frequency of operation and load
- Up to 1.1 Mbit single instance
- Up to 288 bit word
- Up to 16K words deep
- Multiple pin placement and layer options
- Multiple power ring metal layer and configuration options
- Register output options
- Pos. or Neg. Clock Edge
- Multiple output drive strengths
- Different power ring design configurations
- Power ring based on frequency
- Power Mesh on different Metal layers
- Bit Write Mask, Byte Write or Word (global write) options
- Write through, transparent write
- BIST Mux option on inputs
- Row redundancy (RAMpiler+®)
- Column I/O redundancy (RAMpiler+®)
- ECC enabled and capable (SEC, SECDED, OP, EP)
- Front End views are available under NDA
Ultra Low Leakage SRAM
- Description
- Design Status
- Silicon Status
Single Port Memory Compilers
- Synchronous reads/writes
- Static design with zero standby current (except transistor leakage)
- Ability to compile to multiple aspect ratios
- RAMpiler+® with row and column redundancy of up to 2 quad rows & 2 columns I/O
- No restriction and Fully routable over the array with higher metal layers
- Small set-up and zero hold times
- Power ring size based on frequency of operation and load
- Up to 1.1 Mbit single instance
- Up to 288 bit word
- Up to 16K words deep
- Multiple pin placement and layer options
- Multiple power ring metal layer and configuration options
- Register output options
- Pos. or Neg. Clock Edge
- Multiple output drive strengths
- Different power ring design configurations
- Power ring based on frequency
- Power Mesh on different Metal layers
- Bit Write Mask, Byte Write or Word (global write) options
- Write through, transparent write
- BIST Mux option on inputs
- Row redundancy (RAMpiler+®)
- Column I/O redundancy (RAMpiler+®)
- ECC enabled and capable (SEC, SECDED, OP, EP)
- Front End views are available under NDA
Dual Port Memory Compilers
- Synchronous reads/writes
- Static design with zero standby current (except transistor leakage)
- Ability to compile to multiple aspect ratios
- RAMpiler+® with row and column redundancy of up to 2 quad rows & 2 columns I/O
- No restriction and Fully routable over the array with higher metal layers
- Small set-up and zero hold times
- Power ring size based on frequency of operation and load
- Up to 1.1 Mbit single instance
- Up to 288 bit word
- Up to 16K words deep
- Multiple pin placement and layer options
- Multiple power ring metal layer and configuration options
- Register output options
- Pos. or Neg. Clock Edge
- Multiple output drive strengths
- Different power ring design configurations
- Power ring based on frequency
- Power Mesh on different Metal layers
- Bit Write Mask, Byte Write or Word (global write) options
- Write through, transparent write
- BIST Mux option on inputs
- Row redundancy (RAMpiler+®)
- Column I/O redundancy (RAMpiler+®)
- ECC enabled and capable (SEC, SECDED, OP, EP)
- Front End views are available under NDA
High Density SRAM
- Description
- Design Status
- Silicon Status
Single Port Memory Compilers
- Synchronous reads/writes
- Static design with zero standby current (except transistor leakage)
- Ability to compile to multiple aspect ratios
- RAMpiler+® with row and column redundancy of up to 2 quad rows & 2 columns I/O
- No restriction and Fully routable over the array with higher metal layers
- Small set-up and zero hold times
- Power ring size based on frequency of operation and load
- Up to 1.1 Mbit single instance
- Up to 288 bit word
- Up to 16K words deep
- Multiple pin placement and layer options
- Multiple power ring metal layer and configuration options
- Register output options
- Pos. or Neg. Clock Edge
- Multiple output drive strengths
- Different power ring design configurations
- Power ring based on frequency
- Power Mesh on different Metal layers
- Bit Write Mask, Byte Write or Word (global write) options
- Write through, transparent write
- BIST Mux option on inputs
- Row redundancy (RAMpiler+®)
- Column I/O redundancy (RAMpiler+®)
- ECC enabled and capable (SEC, SECDED, OP, EP)
- Front End views are available under NDA
Dual Port Memory Compilers
- Synchronous reads/writes
- Static design with zero standby current (except transistor leakage)
- Ability to compile to multiple aspect ratios
- RAMpiler+® with row and column redundancy of up to 2 quad rows & 2 columns I/O
- No restriction and Fully routable over the array with higher metal layers
- Small set-up and zero hold times
- Power ring size based on frequency of operation and load
- Up to 1.1 Mbit single instance
- Up to 288 bit word
- Up to 16K words deep
- Multiple pin placement and layer options
- Multiple power ring metal layer and configuration options
- Register output options
- Pos. or Neg. Clock Edge
- Multiple output drive strengths
- Different power ring design configurations
- Power ring based on frequency
- Power Mesh on different Metal layers
- Bit Write Mask, Byte Write or Word (global write) options
- Write through, transparent write
- BIST Mux option on inputs
- Row redundancy (RAMpiler+®)
- Column I/O redundancy (RAMpiler+®)
- ECC enabled and capable (SEC, SECDED, OP, EP)
- Front End views are available under NDA
High Density RF
- Description
- Design Status
- Silicon Status
Single Port Memory Compilers
- Synchronous reads/writes
- Static design with zero standby current (except transistor leakage)
- Ability to compile to multiple aspect ratios
- RAMpiler+® with row and column redundancy of up to 2 quad rows & 2 columns I/O
- No restriction and Fully routable over the array with higher metal layers
- Small set-up and zero hold times
- Power ring size based on frequency of operation and load
- Up to 1.1 Mbit single instance
- Up to 288 bit word
- Up to 16K words deep
- Multiple pin placement and layer options
- Multiple power ring metal layer and configuration options
- Register output options
- Pos. or Neg. Clock Edge
- Multiple output drive strengths
- Different power ring design configurations
- Power ring based on frequency
- Power Mesh on different Metal layers
- Bit Write Mask, Byte Write or Word (global write) options
- Write through, transparent write
- BIST Mux option on inputs
- Row redundancy (RAMpiler+®)
- Column I/O redundancy (RAMpiler+®)
- ECC enabled and capable (SEC, SECDED, OP, EP)
- Front End views are available under NDA
Dual Port Memory Compilers
- Synchronous reads/writes
- Static design with zero standby current (except transistor leakage)
- Ability to compile to multiple aspect ratios
- RAMpiler+® with row and column redundancy of up to 2 quad rows & 2 columns I/O
- No restriction and Fully routable over the array with higher metal layers
- Small set-up and zero hold times
- Power ring size based on frequency of operation and load
- Up to 1.1 Mbit single instance
- Up to 288 bit word
- Up to 16K words deep
- Multiple pin placement and layer options
- Multiple power ring metal layer and configuration options
- Register output options
- Pos. or Neg. Clock Edge
- Multiple output drive strengths
- Different power ring design configurations
- Power ring based on frequency
- Power Mesh on different Metal layers
- Bit Write Mask, Byte Write or Word (global write) options
- Write through, transparent write
- BIST Mux option on inputs
- Row redundancy (RAMpiler+®)
- Column I/O redundancy (RAMpiler+®)
- ECC enabled and capable (SEC, SECDED, OP, EP)
- Front End views are available under NDA
Specialty Memory
- Description
- Design Status
- Silicon Status
Read Only Memory Compilers
- Diffusion ROM compiler
- Via Programmable ROM compiler
- Front End views are available under NDA
Content Addressable Memory Compilers
- Binary BCAM, Ternary TCAM, and CAM compilers using CAMpiler® technology
- Front End views are available under NDA
Specialty Memory
- Custom Register Files with different configurations such as: 1W/4R, 3W/3R, 1W/8R, 2W/4R, 3W/5R, etc.
- Front End views are available under NDA