DDR PHY
TSMC 55GP - Hardened DDR & LPDDR PHY
Dolphin's hardened DDRx SDRAM PHY and LPDDRx SDRAM PHY IP is a silicon-proven, Combo PHY supporting speeds up to 1600 Mbps. It is fully compliant with the DFI 4.0 specification, and features include slew rate control, per-bit de-skew, gate training, read
and write leveling and built-in self test (BIST).
In addition, our PHY IP is optimized to provide a complete solution when combined with Dolphin's DDRx and LPDDRx SDRAM Memory Controller IP.
Download Product Overview
- Features
- Design Status
- Silcion Status
- Dolphin DDR2/DDR3 PHY IP is fully compliant with the DFI 4.0 Specification
- Support speeds of up to 1600Mbps with 1.8V and 2.5V Oxide.
- IP is split into 2 hard macros.
One for commands, control and address pins and another for 8-bit data bus.
Can support custom number of address bits. - Compensation controller and Pads are provided for automatic driver and receiver termination impedance calibration
- Features include slew rate control, Per-bit de-skew, gate training, read and write leveling.
- JTAG signals also provided for Mentor/Synopsys and LogicVision
- Built in Self Test with a Pseudo Random Pattern Generator
- Built with Scannable flops
- Can be used in wirebond, flip-chip and cup configurations
- Front End views are available under NDA
- REQUEST NDA
- In production